1. Field
The present disclosure relates to the prevention and/or inhibition of reverse engineering of digital integrated circuits. More particularly, it relates to a multilayered integrated circuit comprising extraneous conductive traces or lines to confuse the reverse engineer, to a process of making a multilayered integrated circuit comprising a step of forming extraneous conductive traces or lines and to a method of designing a multilayered electronic circuit.
2. Description of the Related Art
Modern integrated circuits are constructed such that the signal is routed via metallic lines between blocks such as circuit blocks, logic blocks or memory blocks, or sometimes between transistors within a single block, and to I/O ports. For purposes of compaction, more than one metal layer is used, the two or more layers being separated, for example, by deposited oxide or low-k dielectric materials. These metal lines often comprise a cross-hatched appearance when viewed from the top of the circuit.
FIG. 1 shows a prior art connection between metal traces on different layers. Metal traces 1 and 2 are located on an upper or first layer, while metal trace 3 is located on a lower or second layer. An electrical path between trace 1 and trace 2 is formed by means of conductive via holes 4, 5 filled with metal. The via holes 4, 5 are located within an intermediate layer between the upper layer and the lower layer. The intermediate layer comprising the via holes 4, 5 is usually made of oxide or low-k dielectric material and is typically 1 micrometer thick. The upper, intermediate, and lower layers are not shown in the figure, for clarity purposes.
FIG. 2 shows a schematic plan view of the prior art shown in FIG. 1.
Typically, lines formed from a particular metal layer are routed in parallel along so-called routing or wiring channels. Usually, the routing channels are not filled. Integrated circuits can have a variable number of metal layers, there is no fixed number for all cases.
The design, development and manufacturing efforts pertaining to semiconductor integrated circuits involve the understanding of complex structures, processes and manufacturing techniques involving smaller and smaller electronic circuitry. Efforts to achieve such understanding and establish successful design, development and production manufacturing of such integrated circuits involve many man-hours of highly skilled professionals and considerable expense.
On the other hand, to avoid costly man-hours and other significant expenses some developers resort to reverse engineering practices wherein existing devices are taken apart, probed and otherwise examined to determine the physical structures of the resultant integrated circuit for subsequent copying. This reverse engineering, which typically relies primarily on obtaining a planar optical image of the circuit and, in essence, attempts to by-pass typical product development efforts and expenses by studying and copying a competitive product.
Various approaches can be utilized to prevent reverse engineering of semiconductor integrated circuits. For example, some of the inventors of the present invention have developed concepts taught in U.S. Pat. Nos. 5,866,933, 5,783,846, 5,973,375, and 6,117,762 in which normal metal connections between transistor active areas and contacts are buried in the semiconductor substrate.
These hidden interconnections are typically utilized to replace a good portion of the metal interconnections that would occur in the metal layer nearest the substrate. The use of these hidden interconnectors significantly complicates the reverse engineering because visual inspection of the metal patterns no longer suffices, so that etching and carefully recording each layer down to the substrate is required. Moreover, resolution to within the process-minimum feature size is required of etchant stains that are selective to delineate n- versus p- implants.
The composite of these techniques means that the reverse engineer must provide careful analysis of each transistor and its connections, a process that involves literally millions of steps for even a moderately complex integrated circuit. If this indeed becomes necessary for the reverse engineer, then the task is time consuming and costly. As a result the reverse engineer tries to find ways to automate the process, finding replicated patterns of tricks which are then loaded into a database that identifies, catalogues and places the appearances of similar circuit blocks throughout the circuit.